CoaXpress Camera Side IP core
- Functions
- This is a CoaXpress V1.1 compliant IP core.
This standard uses coaxial cable up to 6.25Gbps (actual rate 5Gbps) per lane.
Data rate can be increased up to 25Gbps with a 4 lane setup.
Cable length can be scaled from 40m ~ over 100m. Installation is not limited by distance.
This IP core implements parts in need of performance as hardware and parts that require flexibility as software on CPU in FPGA, satisfying both needs effectively.
- Features
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- Supports sending stream packet, sending/receiving control packet, receiving trigger packet.
- Auto idle insertion realizes image sending without frame buffer.
- Using high speed transceiver in FPGA reduces PCB size
- Minimum resources (4000LCs at 1lane)
- Link speed can be changed from 1.25Gbps to 6.25Gbps
- Supports 1, 2, 4 lanes.
- Block Diagram
- Supported FPGA
- Xilinx®: Spartan®-6LXT(Up to 3.125Gbps), Kintex®-7, Virtex®-7, Artix®-7
Altera®: Cyclone® IV, Cyclone® V, Arria® II, Arria® V, Stratix® IV, Stratix® V - Performace
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- 6.25Gbps×4 lanes
- AVAL DATA Frame Grabber APX-3664
- 4096×4096 8bit monochrome image sending continuously
- 4096×4096×8bit×146fps=19.6Gbps - Efficiency 98%
- Evaluation Platform
- Evaluation and development is possible by using KC705, SP605, etc.
Please inquire for more details. - Product Number, Licensing
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This IP core is provided by netlist site license or source code site license.
Both licenses have permanent usage rights with limited update support.
Product includes : VHDL source code or netlist, reference design with VHDL source and MicroBlaze or NIOS design.
Permanent netlist site license. Netlist is provided.
Device family is limited.
6 month update support.DC-CXP-L1-NET-XXX 1 lane implementation
DC-CXP-L4-NET-XXX 4 lane implementation※XXX is replaced by device family name.
Example: For Kintex-7, croduct number is DC-CXP-L1-NET-K7. Please inquire for more details.
This license can be used for any devices in same family.Permanent source code site license.
Source codes are provided.
1 year update support.DC-CXP-L4-SRC 4 lane implementation
※1 lane and 2 lane implementation are not sale in this license.
Source codes for all supported devices will be privided. Please inquire for unsupported devices. - Pamphlet Download
- CoaXpress IP Core Product Brief
- Reference Design Guide Download
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Actual reference design for camera function is also provided.
CoaXpress IP Core Reference Design Guide